In general, a semiconductor memory device includes a plurality of clock paths to transfer a clock signal to internal circuits, and each of the internal circuits uses the clock signal transferred through a corresponding clock path.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device.
As shown, a semiconductor memory device enables a clock input buffer to buffer a clock signal CLK applied through a pad, and transfers the clock signal to a first clock path CLK PATH1, a second clock path CLK PATH2 and a write clock path WRITE CLK PATH. The clock signal CLK transferred through the first and second clock paths CLK PATH1 and CLK PATH2 is provided to a first internal circuit 130 and a second internal circuit 140, and is used in corresponding internal circuits.
Moreover, the semiconductor memory device has a data input control unit 110 and a data input driving unit 120. The data input control unit 110 compares a data alignment signal ALIGN_S with the clock signal CLK_W transferred through the write clock path WRITE CLK PATH, and generates a data input enable signal DINSTBP. The data input driving unit 120 transfers aligned input data signals DATA_IN<1:N>, which are outputted from a data input buffer, to a data transfer line GLOBAL DAT LINE in response to the data input enable signal DINSTBP.
An operation of the conventional semiconductor memory device mentioned above will be described below.
The data input control unit 110 compares the data alignment signal ALIGN_S with the clock signal CLK_W transferred through the write clock path WRITE CLK PATH, and generates the data input enable signal DINSTBP. The data alignment signal ALIGN_S is enabled when the input data signals DATA_IN<1:N> applied from an external source are buffered by the data input buffer and aligned in parallel.
The data input driving unit 120 transfers the input data signals DATA_IN<1:N>, which are aligned in response to the data input enable signal DINSTBP, to a data transfer line GLOBAL DATA LINE.
As mentioned above, the conventional semiconductor memory device produces a dynamic current consumption of the clock signal because the clock signal CLK_W provided to the data input control unit 110, which generates the data input enable signal DINSTBP, is consecutively toggled.
Since the dynamic current produced by the toggling of the clock signal is increased in proportion to a frequency when the frequency of the clock signal is increased to improve a performance of the semiconductor memory device, it is necessary to reduce a current consumption produced by the clock signal.